1. Field of the Invention
The present invention relates to wafer processing, and more particularly to improving the wafer processing using multi-dimensional targets.
2. Description of the Related Art
Many multiple patterning techniques are currently being use during semiconductor wafer processing to increase the number of features and/or structures within devices on a wafer. Multiple patterning techniques can include double exposure techniques, double patterning techniques, spacer techniques, mask techniques, and brute force techniques. In 2006, the International Technology Roadmap for Semiconductors was expanded to include double patterning as a potential solution for 32 nm (nanometer) lithography. Multiple patterning techniques are viewed by some device manufacturers as bridge solutions that can be used until Extreme Ultra-Violet (EUV) techniques become more fully developed.